1. Field of the Invention
The present invention relates to a semiconductor integrated circuit capable of replacing a defective memory cell with a redundant cell and a checking method for checking whether replacement with a redundant cell. is correctly performed.
2. Related Art
There are known SRAMs capable of replacing a defective memory cell with a redundant cell to improve yield (see JP-A 7-272411 (Kokai) and JP-A 1-23465 (Kokai)).
In a semiconductor integrated circuit including an SRAM of this type, a so-called die sort test is first performed at the wafer level. If any defective cell is found in the SRAM at the time of the die sort test, it is checked with a tester whether a redundancy control circuit incorporated in the SRAM can relieve the defective cell. If the redundancy control circuit can relieve the defective cell, redundancy information for relieving the defective cell is stored in the tester.
A die sort test is usually performed for each lot, which is composed of a plurality of wafers. Pieces of redundancy information of all chips included in one lot are collectively outputted at the end of a die sort test for the lot. The outputted redundancy information is associated with chip IDs identifying chips and saved in a predetermined file.
After that, a blowing step is performed for each lot. In the blowing step, fuses corresponding to defective cells in chips are blown by laser based on the redundancy information obtained from the die sort test.
Generally, a device which performs the blowing step does not have the function of confirming whether a fuse is correctly programmed (blown). Accordingly, when the blowing step is performed, there is no way of knowing whether fuses are programmed as intended.
After the blowing step, wafers are diced, encapsulated in packages, and sent to a final test step. After a chip is sealed off, it is impossible to know to which lot the chip belongs, where in the sequence of wafers of the lot a wafer having the chip is located, and at which position on the wafer the chip is present, without reading out its chip ID. If a chip ID is correctly read out, the redundancy information of a semiconductor integrated circuit corresponding to the chip ID can be acquired from the above-described file, and a defective cell can be correctly identified.
However, if a read-out chip ID is incorrect, the redundancy information of a different semiconductor integrated circuit is read out from the file, and a semiconductor integrated circuit having a defective cell cannot be identified. Accordingly, the final test step may not be correctly performed or the time until the final test step ends may become longer.